FIG. 13 is a block diagram illustrating a semiconductor integrated circuit which constitutes a prior art clock generation apparatus for generating a synchronous clock for a signal which is input at a fixed rate.
As shown in this figure, the semiconductor integrated circuit 1300 constituting the prior art clock generation apparatus comprises an analog input terminal 1301, a threshold input terminal 1302, a synchronous signal output terminal 1303, a synchronous clock output terminal 1304, a comparator circuit 1305, a clock supply circuit 1306, a counter circuit 1307, a decoder circuit 1308, an edge detection circuit 1309 and a D-type flipflop 1310.
The comparator circuit 1305 is a circuit for comparing an analog signal S1301 with the level of a threshold S1302 and outputting the result of the comparison as a binarized signal, i.e., a comparison signal S1305. The comparator circuit 1305 operates using a clock supplied by an oscillator circuit in the clock supply circuit 1306 as the reference clock.
The clock supply circuit 1306 is realized by a crystal oscillator circuit using a crystal or the like. The frequency of the clock which is output by the clock supply circuit is an integral multiple of the rate at which the analog signal S1301 is input. In addition, the edge detection circuit 1309 is a circuit for detecting the edge of the comparison signal S1305 which is output by the comparator circuit 1305. The signal which has been subjected to the edge detection is supplied to the counter circuit 1307.
The counter circuit 1307 operates using the clock signal S1306 from the clock supply circuit 1306 as the reference clock. The count value output by the counter circuit 1307 is supplied to the decoder circuit 1308. The counter circuit 1307 operates using the output from the edge detection circuit 1309 and the output from the decoder circuit 1308 as the clear signals.
Hereinafter, the operation of the digital PLL device will be described.
Initially, the analog signal S1301 and the threshold S1302 are input to the comparator circuit 1305 via the analog input terminal 1301 and the threshold input terminal 1302, respectively.
The comparator circuit 1305 makes the comparison to see whether the level of the analog signal S1301 is larger or smaller than the threshold S1302, and outputs the result of the comparison.
A binarized comparison signal S1305 output by the comparator circuit 1305 is input to the edge detection circuit 1309, and the edge of the comparison signal S1305 is detected herein. The signal whose edge was detected is supplied to the counter circuit 1307 and clears the counter.
Owing to the series of operations of edge detection and counter clear, the count value of the counter circuit 1307 and the edge, i.e., phase of the comparison signal S1305, match.
The count value of the counter circuit 1307 is usually composed of plural bits. Therefore, the decoder circuit 1308 executes decoding so as to output a sample clock signal S1304 and strobe the analog input signal S1301 in an appropriate phase. The D-type flipflop 1310 stably latches the comparison signal S1305 with supply of a sample clock signal S1304 which is output by the decoder circuit 1308.
As described above, in the semiconductor integrated circuit 1300 constituting the prior art clock generation apparatus, a clear signal S1308 for clearing the count value of the counter circuit 1307 decides the frequency division ratio of the counter circuit 1307. The D-type flipflop 1310 stably latches the comparison signal S1305 with the sample clock signal S1304 which is output by the decoder circuit 1308. Therefore, the semiconductor integrated circuit 1300 outputs a synchronous signal and a synchronous clock, which are stable toward the variations in outside environments, such as the variations in temperature or supply voltage and variations with time.
However, in the semiconductor integrated circuit constituting the prior art clock generation apparatus, the frequency of an oscillated clock S1306 which is supplied by the clock supply circuit 1306 is an integral multiple of the input rate of the analog signal S1301, and the variations in the count value of the counter circuit 1307 directly result in the resolution showing the phase of the input analog signal S1301. Therefore, the error in the phase which occurs in the counter circuit 1307 results in the phase error in the case where the signal is captured by the D-type flipflop 1310. In order to solve this problem, the only way is to increase the frequency of the clock supply circuit 1306 to improve the performance. Further, when this is implemented and an extremely high frequency is selected as the frequency of the clock supply circuit 1306, unnecessary radiation is generated from the semiconductor integrated circuit.
Further, in the semiconductor integrated circuit constituting the prior art clock generation apparatus, in the case where the oscillated clock s1306 is not an integral multiple of the input rate of the analog signal S1301, when the input signal S1301 is kept in a certain condition during a period longer than the cycle of the oscillated clock S1306 (for example, when the high level continues), the phase error for the input signal finally exceeds the tolerance and the input signal is erroneously recognized. This results in limiting the frequency of the oscillated clock which is used in the semiconductor integrated circuit comprising the prior art clock generation apparatus. Accordingly, when the input signal has plural kinds of input rates, plural oscillator circuits which correspond to respective input rates are required.